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AT73C240
7.4
Timing Specifications
The timing constraints of the data interface are described in Figure 7-7 and Table 7-2 below.
Figure 7-7.
Data Interface Timing Diagram
1
20
M/2+1
M
BCLK
LRFS
SDIN
ts1
ts2
th1
th2
Table 7-2.
Data Interface Timing Parameters
ts1
th1
ts2
th2
Parameter
LRFS set-up time before BCLK rising edge
LRFS hold time after BCLK rising edge
DIN set-up time before BCLK rising edge
DIN hold time after BCLK rising edge
Min
10
10
10
10
Typ
Max
Unit
ns
ns
ns
ns
7.5
SMODE Selection
SMODE input is internally pulled up in the AT73C240. This ensures a TWI communication proto-
cole default mode
When setting SMODE to 0, SPI communication protocol can also be used.
Two cases have to be considered:
SMODE=1, TWI protocole
SMODE=0, SPI protocole
11
6464A–PMAAC–28-Apr-09
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